This invention relates to methods of and apparatus for reducing of electromagnetic interference emitted by a circuit. More particularly, the invention relates to methods of and apparatus for reducing electromagnetic interference emitted by a clock circuit.
Many devices have logic integrated circuits that use a high frequency clock which, in combination with high frequency harmonics, can create electromagnetic interference in other integrated circuits. The clock can also create electromagnetic interference with radio circuits through an antenna, or other circuits which are not necessarily integrated circuits. This clock is shared with other system elements including circuits outside of the integrated circuit that has the clock. An integrated circuit with logic working at such a frequency will create, on its power supply pins and output signals, a lot of high frequency harmonics of the base clock frequency. These harmonics will spread beyond the integrated circuit that has the clock through wires on a PCB (printed circuit board) on which the integrated circuit having the clock is mounted. Electromagnetic interferences are interferences caused by another source.
Numerous wireless communication standards have been introduced in recent years to accommodate a number of diverse communication applications. Exemplary conventional communication standards include Personal Handy-Phone Systems (PHS) and Digital European Cordless Telephone (DECT) and Global Systems for Mobile Communications (GSM). Such communication protocols provide communication channel slots structured in frames individually containing multiple slots. Data packets are allocated to communication slots in such communication systems. The frame structures are repeated in time and each time the appropriate slot number occurs, the data packet associated with the slot is either transmitted or received.
In a system such as a GSM cellular phone, there is a baseband chip (where base frequency data processing occurs) that has a reference clock. The reference clock is a main clock used on the board, and used to synchronize different elements of the system, but the GSM chip itself (or system) can use other clocks. For the example of a GSM cellular phone, the clock frequency of the reference clock is 13 MHz. In the example of a GSM cellular phone, some of the high order harmonics of the base clock frequency are coincident with some radio channels, and the high frequency noise emitted by the baseband chip running at 13 MHz can be directly picked up by the antenna of the GSM cellular phone from the PCB wires.
More particularly, in a GSM phone, the baseband GSM integrated circuit produces high frequency harmonics on its power supply pins, which create electrical and magnetic fields around the board wires and the integrated circuit. These fields can be picked up by a radio antenna of the GSM phone, as described above, and added to the radio signal as a noise source. These noise sources, if they have peaks located inside GSM phone radio channels, or coincident with radio channels, can in turn be mistaken for actual radio signals.
One solution is to shield the different components on the PCB, plus the PCB wires, but this can be very costly. Less expensive solutions can be developed if emissions of high frequency noise can be reduced.
Attention is directed to the following patents, all of which are incorporated herein by reference: U.S. Pat. No. 5,731,728 issued to Greiss; U.S. Pat. No. 5,488,627 issued to Hardin et al.; U.S. Pat. No. 5,430,392 issued to Matejic; and U.S. Pat. No. 5,263,055 to Cahill. The solutions described in these patents, and other prior art solutions are typically complicated and expensive, often using circuitry such as a radio stage or an oscillator.
GSM is a form of time division multiple access (TDMA) communications. The term GSM, as used herein and in the appended claims, is to be construed as encompassing the PCS standard used in the United States and elsewhere. GSM systems are described in greater detail in the following patents, all of which are incorporated herein by reference: U.S. Pat. No. 5,923,761 to Lodenius; U.S. Pat. No. 5,872,801 to Mobin; U.S. Pat. No. 5,842,037 to Haartsen; U.S. Pat. No. 5,826,181 to Reed; U.S. Pat. No. 5,818,820 to Anderson et al.; U.S. Pat. No. 5,812,590 to Black et al.; and U.S. Pat. No. 5,787,076 to Anderson et al.
This invention provides a simple way to spread the spectrum of the basic clock on a chip, so that its high-frequency components will be flattened. The spectral energy being the same, there will be less frequency peaks that, for example, could fall into a radio channel if the clock is used in a GSM phone. The idea of spreading the spectrum is itself well known, but the way by which it is achieved in accordance with the invention is very simple and economic both in terms of area and power. The invention can, of course, be applied to all the clocks that are distributed in an integrated circuit.
The invention provides a method of producing a clock signal with reduced electromagnetic interference spectral components, the method comprising providing a first clock signal; producing a second clock signal by delaying the first clock signal; and generating a jittered clock signal by switching between the first clock signal and the second clock signal at times selected responsive to a random number generator.
One aspect of the invention provides a method of producing a clock signal that generates reduced electromagnetic interference, the method comprising providing a first clock signal; producing a second clock signal by delaying the first clock signal; and generating a jittered clock signal using a multiplexer to pseudo-randomly switch between the first clock signal and the second clock signal over time. In one aspect of the invention, the multiplexer has multiple additional inputs, and the method further comprises producing multiple additional clock signals, different from the first and second clock signals, and coupling the multiple additional clock signals to respective additional inputs of the multiplexer, and wherein generating a jittered clock signal comprises generating a jittered clock signal by causing the multiplexer to switch between the first clock signal, the second clock signal, and the additional clock signals, to select any one of the time signals, at times selected responsive to a pseudo-random number generator.
Another aspect of the invention provides a method of reducing electromagnetic interference in a GSM phone having a plurality of components that use a clock signal, the method comprising providing a first clock signal; producing a second clock signal by delaying the first clock signal; generating a jittered clock signal by switching between the first clock signal and the second clock signal at times determined responsive to a random number generator; and using the jittered clock signal as a system clock for at least some components of the GSM phone.
Another aspect of the invention provides circuitry for producing a clock signal with reduced electromagnetic interference spectral components, comprising a clock configured to produce a first clock signal; a delay element coupled to the clock to produce a second clock signal by delaying the first clock signal; a multiplexer coupled to the clock and to the delay element to select between the clock and the delay element, the multiplexer having a select input which determines whether the clock or delay element is selected; and a random number generator coupled to the select input, wherein the multiplexer generates a jittered clock signal by switching between the first clock signal and the second clock signal responsive to the random number generator.
Another aspect of the invention provides a GSM phone comprising a clock configured to produce a first clock signal; a delay element coupled to the clock to produce a second clock signal by delaying the first clock signal; a multiplexer coupled to the clock and to the delay element to select between the clock and the delay element; a random number generator coupled to the multiplexer wherein the multiplexer generates a jittered clock signal by switching between the first clock signal and the second clock signal responsive to the random number generator; and a plurality of GSM phone components respectively coupled to the multiplexer to use the jittered clock signal as an input clock for the component.
In one aspect of the invention, the original clock signal is replaced with a jittered clock signal, this jittered clock signal being generated by a multiplexer pseudo-randomly choosing between the original clock or a delayed clock. In simulation, this has shown an improvement of 10 dBm for the simplest implementation on the high-frequency components of the master clock.
The simplest embodiment of the invention requires only one multiplexer, 5 D-type flip-flops, and a few logic gates. This is very simple in comparison with other known methods, such as those shown in U.S. Pat. No. 5,731,728 to Greiss; U.S. Pat. No. 5,263,055 to Cahill; U.S. Pat. No. 5,430,392 to Matejic;, or U.S. Pat. No. 5,488,627 to Hardin et al, all of which are incorporated herein by reference.